1. Field of the Invention
The present invention relates to integrated circuit technology. More specifically, the present invention relates to a packaging and interconnect system for integrated circuits.
2. The Prior Art
Multi-chip modules (MCM) comprising a plurality of integrated circuit dice mounted on a single carrier substrate and a package which provides an interconnect and support function are known in the art. Their use has increased substantially in recent years, and there is an increasing number of applications for MCM technology. The development of MCM devices has required the co-development of suitable mounting and connection technologies. There have been several prior art solutions used to mount and connect die to MCM devices.
According to one prior art approach to mounting a plurality of integrated circuit die on a single MCM substrate, a first multilayer interconnect circuit for interconnecting a plurality of integrated circuit die comprises alternating layers of an insulating material and metal lines and is formed on a first aluminum wafer. The first aluminum wafer carrying the first multilayer interconnect circuit is bonded to a stainless steel circumferential support ring. The first aluminum wafer is etched away, leaving the multilayer interconnect circuit supported by the stainless steel circumferential support ring.
If necessary due to interconnect density, a second multilayer interconnect circuit for interconnecting a plurality of integrated circuit die may be formed on a second aluminum wafer. The second aluminum wafer is bonded to the bottom of the first multilayer interconnect circuit. The second aluminum wafer is then etched away leaving the first and second multilayer interconnect circuits supported by the stainless steel circumferential support ring. Windows for the die to be mounted are cut in the multilayer interconnect circuits and a copper baseplate is bonded to the interconnect circuits. The support ring is then excised from the circuit layers and the die are then mounted on the copper baseplate containing the first and second multilayer interconnect circuits. The die are connected to the interconnect circuitry and to the MCM I/O pads using conventional TAB or wire bonding techniques.
As will be appreciated by those of ordinary skill in the art, this approach requires the use of a separate support ring which must be mated with the assembly in a discrete processing step, and yet another step is required to bond the interconnect circuit to the baseplate. In addition, the mounting of the integrated circuit die directly on the baseplate through apertures formed in the interconnect circuitry layer requires the additional step of forming the apertures prior to bonding the die on the baseplate. The die apertures also consume valuable space which could be used to route circuit traces.
According to another prior-art approach for mounting a plurality of integrated circuit die on a single MCM substrate, a multilayer thin-film interconnect circuit is deposited onto a quartz substrate. The die are then bonded to the thin film interconnect circuit and a circumferential ceramic support ring is bonded to the assembly. The quartz substrate is then removed by etching. Reach-through vias are etched in the thin film circuit to expose the I/O pads on the die and a die interconnect metal layer is formed and defined to interconnect the integrated circuit die. While this solution is useful for MCM technology, it is limited to small circuits and is not reworkable to recover yield losses.
Still another related approach, relating to die testing rather than to permanent MCM mounting techniques, is disclosed in U.S. Pat. No. 5,123,850 to Eider et al. This patent teaches the use of an interconnect circuit formed in a resilient membrane to make temporary electrical contact with pads disposed on a die. The interconnect circuit is formed from alternating layers of polyimide dielectric and metal signal lines. Electrical contact pads protrude from a top surface of the membrane and make electrical contact with individual signal lines. A semiconductor die is placed on the membrane and is aligned by visible means to ensure that the contact pads are disposed opposite pads on the die. An insert plate is placed against a bottom surface of the membrane opposite the die. The interconnect circuit is wire bonded to a pin grid array (PGA) which can be plugged into a test socket base to communicate test signals to and from the carrier. A heat sink is clipped to the PGA, and the die is pressed between the heat sink and the membrane. The force exerted against the die is expected to cause the contact pads to make electrical contact with the die pads.
While earlier chip testing carriers such as the one described above contain good design concepts there have been shortcomings with their use. For example, the gold coated pads on the contact pads often do not make adequate contact with the die pads because of the build-up of an oxide layer on the aluminum die pads.